8 decade multiplexed counter features: ?dc to 7.5 mhz count frequency ?multiplexed bcd and 7 segment outputs ?dc to 500 khz scan frequency ?+4.75v to +15v operation ( v ss - v d d ) ?compatible with cmos logic ?high input noise immunity ?counter output latches ?leading zero blanking ?low power dissipation ?all inputs protected ?40 pin dip - see figure 1 description: ( see block diagram, figure 4.) the ls7030 is a mos, 8 decade up counter. the circuit includes latches, multiplexer, leading zero blanking and 7 segment data outputs. 8 decade up counter the eight decade ripple through counter increments on the neg- ative edge of the input count pulse. maximum ripple time is 12? (99999999 to 00000000). maximum count frequency is 7.5mhz. reset all decades are reset to zero when reset input is brought low for a minimum of 4?. the overflow flip-flop is reset at the same time. reset must be high for a minimum of 1? before next valid count can be recorded. latches contents of counter are transferred to latches when load signal is brought low for a minimum of 4? and kept low until a minimum of 12? has elapsed from previous negative edge of count pulse (ripple time). storage of valid data occurs when load signal is high for a minimum of 1? before next negative edge of count pulse or reset. data is transferred for overflow flip-flop to over- flow latch at the same time. scan oscillator and counter the scan counter is driven by an internal oscillator whose fre- quency is determined by a capacitor connected between os- cillator input and scan input. an external scan clock applied to scan input can also drive the scan counter. scan counter ad- vances on negative edge of scan clock. the counter scans from msd to lsd. when scan reset input is brought high the scan counter is forced to msd state. internal synchonization guarantees proper scanning no matter when scan reset is brought low relative to scan clock. maximum scan frequency is 500khz. decimal point a high at the decimal point input resets the blanking flip-flop causing the display to unblank. decimal point should be brought high at start of digit time which has active decimal point. january 2003 7030 - 012703 - 1 lsi/csi l si c o m p u t e r sy s t e m s , i n c . 12 3 5 w a l t w h i t m a n ro a d , m e l v i l l e , n y 1 174 7 ( 631 ) 2 71 - 0 40 0 f a x ( 631 ) 2 7 1 - 0 4 0 5 ls7030 lsi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 figure 1 connection diagram - top view osc. input scan input lamp test input a b n.c. c d count input e f g test count input, digits 3 - 8 v ss v gg n.c. n.c. v dd reset counter input load latch input scan reset input msd strobe 8 strobe 7 strobe 6 strobe 5 strobe 4 strobe 3 strobe 2 lsd strobe 1 decimal point input blank output overflow output overflow input decade 6 output, d8 decade 7 output, d7 decade 6 output, d6 b8 b4 b2 b1 bcd data outputs digit strobe outputs ls7030 segment outputs segment outputs digit strobes timing of digit strobes is arranged such that both edges of strobe are guardbanded by a minimum 400ns within valid bcd data when scan frequency is 100khz or less. the guardband is a minimum of 200ns at 250khz scan frequency. at 500khz only negative edge of strobe is guaranteed to be within valid bcd data by a minimum 200ns. overflow the overflow flip-flop sets on the first negative transition of the over- flow input and remains set until reset is brought low. data is trans- ferred from overflow flip-flop to overflow latch when load is brought low. a high at the overflow latch causes display to unblank. over- flow output is output of overflow latch. msb outputs of decades 6, 7, 8 are available for use as overflow input. blanking leading zero blanking is employed. at start of each msd to lsd scan, display is blanked until a nonzero digit or active decimal point is encountered. displaly unblanks during lsd time and for a whole scan when overflow output is high. when scan reset is applied, dis- play blanks to prevent display damage. blanking information is available at blank output and is incorporated into 7 segment information. u l a3800
with v gg at -12v, v dd at ov and vss at +5v, all inputs are ttl and cmos compatible. all outputs are cmos compatible and bcd and blank outputs also provide standard ttl compat- ibility. in addition, overflow output is low power ttl compatible. in either mode outputs swing between v dd and vss. maximum ratings parameter symbol value units storage temperature tstg -65 to +150 ? operating temperature t a -25 to +70 ? voltage (any pin to vss) vmax -30 to +0.5 v parameter symbol min max units operating supply current idds - 15 ma (f c = 7.5mhz) input noise immunity low and high vni 25% - v (vss - v dd ) test count input vil vss - 20 vss - 3.95 v vih vss - 1.0 vss v output voltage ?" vol - +0.2 v output voltage ?" voh vss - 1.0 - v output voltage ?" (sinking 10?) vol - +0.5 v output voltage ?" vss = 4.75 (voh = vss - 0.5v) - 0.05 - ma (voh = vss - 1v) - 0.25 - ma (voh = vss - 4v) - 0.90 - ma vss = 10v (voh = vss - 2v) - 2.0 - ma (voh = vss - 3v) - 3.0 - ma vss = 15v (voh = vss - 2v) - 3.0 - ma (voh = vss - 3v) - 4.5 - ma note 1 : current sink = same as segment and strobe outputs. current source = n/a at voh = vss - 0.5v for vss = +4.75v 35? at voh = vss - 1v for vss = +4.75v 40% of segment and strobe outputs at all other specified operating points. note 2 : limit segment current to 4.5ma maximum. limit strobe current to 6ma maximum. the following inputs have internal pull down resistors to v dd with maximum sink current of 5? at vss input. scan reset test count count decimal point overflow lamp test dc electrical characteristics (v dd = v gg = ov, vss = +4.75 to +15v, -25? t a 3 +70? unless otherwise specified.) d6, d7, d8 of, bcd blank (see note 1 ) segment and strobe outputs (see note 2) bcd and 7 segment data data is available in bcd and 7 segment format. bcd data can be demultiplexed using digit strobes as latch enable signals. power supplies +4.75 volts to +15 volts single power supply operation is obtained when v gg and v dd are tied together. inputs and outputs are cmos compatible and minimum input noise immunity of 25% of power supply is guaranteed except for test count input. (inputs are ttl compatible at +4.75v to +5.25v operation.) scan oscillator capacitance typical oscillator frequency 4.75v 10v 15v 50pf 40.0 khz 24.2khz 22.2 khz 100pf 22.2 khz 14.8khz 13.8 khz 470pf 5.0 khz 3.6khz 3.5 khz 750pf 3.3 khz 2.4khz 2.2 khz 2000pf 1.3 khz 0.91khz 0.85 khz { 7030-012703-2
electrical characteristics : (v dd = v gg = ov, vss = +4.75 to +15v, -25?c t a +70?c unless otherwise specified.) parameter symbol min max units count test and count frequency (vss = +5v ?5%) f c , f tc dc 7.5 mhz (vss = +10v) f c , f tc dc 6 mhz (vss = +15v) f c , f tc dc 5 mhz scan frequency f sc dc 500 khz count pulse width (vss = +5v ?5%) t cpw 66 - ns (vss = +10v) t cpw 83 - ns (vss = +15v) t cpw 100 - ns count ripple time t cr - 12 ? load pulse width t lpw 4 - ? load removal tme t lr - 1 ? reset pulse width t rpw 4 - ? reset removal time t rr - 1 ? rise and fall time count pulse t rfc - 4 ? reset pulse t rfr - 4 ? test count pulse t rftc - 80 ? *strobe guard band time t gb 400 - ns (f sc 100khz) *strobe guard band time t gb 200 - ns (100khz f sc 250khz) *strobe guard band time t gb 200 - ns (250khz f sc 500khz) negative edge only figure 2. guard banded strobe bcd strobe t gb t gb f b a g d e c figure 3. seven segment font ttl compatible outputs: power supplies: vss = +5v ?5%, v dd = 0v, v gg = -12v ?5% output levels: ?" level 3 vss - 0.5v (sourcing 100?) ?" level 0.4v (sinking 1.6ma) ?" level 3 vss - 0.5v (sourcing 40?) ?" level 0.4v (sinking 0.18ma) all other outputs as specified for single power supply, vss = + 15v, operation. inputs as specified for single power supply, vss = +5v ?5% operation. } } blank and bcd data outputs overflow output the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7030-012703-3
1 2 4 8 bcd counter r c 1 2 4 8 bcd counter r c 1 2 4 8 bcd counter r c 1 2 4 8 bcd counter r c 1 2 4 8 bcd counter r c 1 2 4 8 bcd counter r c 1 2 4 8 bcd counter r c 1 2 4 8 bcd counter r c 4 bit latch st 4 bit latch st 4 bit latch st 4 bit latch st 4 bit latch st 4 bit latch st 4 bit latch st 4 bit latch st 1 2 4 8 b1 b2 b4 b8 b1 b2 b4 b8 b1 b2 b4 b8 b1 b2 b4 b8 b1 b2 b4 mux gate g b8 segment decoder data output buffer seven d6 output d7 output d8 output ovflw f/f overflow input 1 bit latch bcd data output blank out lamp test input vss v gg v dd overflow output st blanking f/f s r q c r nz 8 digit strobe outputs output buffers 8 state static scan counter & decoded lsd msd r c oscillator or buffer scan reset input (reset to msd) figure 4. ls7030 block diagram osc. input scan input 2 1 3 4 5 6 7 8 test count input reset input load latch input 1 2 4 8 mux gate g 1 2 4 8 mux gate g 1 2 4 8 mux gate g 1 2 4 8 mux gate g 1 2 4 8 mux gate g 1 2 4 8 mux gate g 1 2 4 8 mux gate g count input seven segment data out 22 40 39 lsd msd decimal point input 10 27 26 23 11 17 18 19 20 37 36 34 33 31 30 29 38 12 13 14 15 16 28 32 21 9 8 7 6 5 4 3 2 1 b1 b2 b4 b8 a b c d e f g 7030-012703-4
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